Reverse-Order Source/Drain with Double Offset Spacer Design Optimization for Sub-50-nm Low-Power MOSFETs

We optimized a RODOS (reverse-order source/drain formation with double offset spacer) structure in terms of the gate delay (CV/I) and the switching energy (CV). Simulations confirmed that the poly-Si depletion effect, the DC characteristics, the gate delay and the switching energy were enhanced. In the case of 50-nm nMOSFETs, they showed a 794-μA/μm on-current, a 0.1-nA/μm off-current, a 65-mV/V DIBL (drain induced barrier lowering), an 80-mV/dec SS (subthreshold slope), a 1.29-ps CV/I, and a 0.151-fJ CV. Finally, they confirmed that the RODOS MOSFET was a good approach to a planar MOSFET structure for mobile appliances.